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AES Fast Core

AES Core Pinout

Overview

The AES Fast IP Core provides a balance between high throughput and size for the Advanced Encryption Standard (AES) block cipher. The Fast IP core comes with a 128-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need high throughput, low latency, and reduced power consumption. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.

The AES Fast IP core is available in encrypt, decrypt, and encrypt/decrypt versions.

Performance

The table below shows the logic resource and performance figures for the AES Fast IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  AES Fast IP Core (Encryption Only)
technology Xilinx
Spartan 6-3
Altera
Stratix III-C2
Xilinx
Virtex 6-3
logic resources 381 slices
0 blockram
427 ALMs
15 M9K
364 slices
0 blockram
max clock 256 MHz 288 MHz 427 MHz
max throughput
(128-bit key)
2978 Mbps 3351 Mbps 4968 Mbps

 

Ordering Information

The AES Fast IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Fast Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements AES block cipher specified by NIST FIPS 197
  • Synchronous 128-bit IO interfaces
  • Integrated key expansion supporting 128, 192, and 256-bit key lengths
  • High throughput requires only 11, 13, and 15 clock cycles per encryption
  • Small hardware footprint for reduced power consumption
  • Quick key wipe for anti-tamper applications
Suitable for implementation in:
  • Confidentiality: CBC, CFB, CTR, OFB, and XTS-AES
  • Authentication: CMAC
  • Authenticated Encryption: CCM and GCM
Applications
  • IPSec, Secure eCommerce (TLS/SSL), WLAN, Digital Rights Management (DRM), Data Storage Encryption (IEEE P1619), Hardware Security Tokens
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation

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