• Home
  • Products
  • Services
  • Support
  • Company
Products
Home Products AES Standard IP Core

AES Standard Core

AES Core Pinout

Overview

The AES Standard IP Core provides a simple and compact hardware solution for the Advanced Encryption Standard (AES) block cipher. The Standard IP core comes with a 32-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need both moderate throughput and reduced power consumption. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.

The AES Standard IP core is available in encrypt, decrypt, and encrypt/decrypt versions.

Performance

The table below shows the logic resource and performance figures for the AES Standard IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  AES Standard IP Core (Encryption Only)
technology Xilinx
Spartan 6-3
Altera
Stratix III-C2
Xilinx
Virtex 6-3
logic resources 135 slices
0 blockram
201 ALMs
7 M9K
132 slices
0 blockram
max clock 246 MHz 296 MHz 434 MHz
max throughput
(128-bit key)
715 Mbps 861 Mbps 1262 Mbps

 

Ordering Information

The AES Standard IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Standard Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements AES block cipher specified by NIST FIPS 197
  • Synchronous 32-bit IO interfaces
  • Integrated key expansion supporting 128, 192, and 256-bit key lengths
  • High throughput requires only 44, 52, and 60 clock cycles per encryption
  • Small hardware footprint for reduced power consumption
  • Quick key wipe for anti-tamper applications
Suitable for implementation in:
  • Confidentiality: CBC, CFB, CTR, OFB, and XTS-AES
  • Authentication: CMAC
  • Authenticated Encryption: CCM and GCM
Applications
  • IPSec, Secure eCommerce (TLS/SSL), WLAN, Digital Rights Management (DRM), Data Storage Encryption (IEEE P1619), Hardware Security Tokens
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation

Copyright © 2017 Mercora Technologies, LLC.    |    Home    |    Products    |    Services    |    Support    |    Export    |    Company    |    Feedback