Overview
The AES Standard IP Core provides a simple and compact hardware solution for the Advanced Encryption Standard (AES) block cipher. The Standard IP core comes with a 32-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need both moderate throughput and reduced power consumption. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
The AES Standard IP core is available in encrypt, decrypt, and encrypt/decrypt versions.
Performance
The table below shows the logic resource and performance figures for the AES Standard IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
| AES Standard IP Core (Encryption Only) | |||
| technology | Xilinx Spartan 6-3 |
Altera Stratix III-C2 |
Xilinx Virtex 6-3 |
| logic resources | 135 slices 0 blockram |
201 ALMs 7 M9K |
132 slices 0 blockram |
| max clock | 246 MHz | 296 MHz | 434 MHz |
| max throughput (128-bit key) |
715 Mbps | 861 Mbps | 1262 Mbps |
Ordering Information
The AES Standard IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..