Overview
The AES Ultra Fast IP Core provides the ultimate in performance for the Advanced Encryption Standard (AES) block cipher. The Ultra Fast IP core comes with a 128-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. Using Mercora Technologies intelligent pipe management architecture the core can be scaled in size and speed depending on the throughput requirements. The core is designed for applications that need high throughput and low latency. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
The AES Ultra Fast IP core is available in encrypt, decrypt, and concurrent encrypt/decrypt versions.
Performance
The table below shows the logic resource and performance figures for the AES Ultra Fast IP Core with 4, 7, and 10 intelligent pipe management rounds. The number of rounds can be reconfigured to any number between 1 and 10. Additional chipset figures as well as an operational data sheet are available upon request.
| AES Ultra Fast IP Core (Encryption Only) | |||
| technology | Xilinx Virtex 6-3 |
Xilinx Virtex 6-3 |
Xilinx Virtex 6-3 |
| intelligent pipe managment |
4 rounds | 7 rounds | 10 rounds |
| logic resources | 1373 slices 0 blockram |
1838 slices 0 blockram |
2320 slices 0 blockram |
| max clock | 382 MHz | 395 MHz | 357 MHz |
| max throughput (128-bit key) |
19,558 Mbps | 35,392 Mbps | 45,696 Mbps |
Ordering Information
The AES Ultra Fast IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..