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HMAC SHA-1 Core

HMAC SHA-1 Core Pinout

Overview

The HMAC SHA-1 Fast IP Core provides a hardware implementation of the Keyed-Hash Message Authentication Code (HMAC) for the SHA-1 hash algorithm. The Fast IP Core provides a balance between high throughput and size and comes with a 32/160-bit IO interface. The HMAC SHA-1 can accept messages up to 264-512 bits in length and returns a 160-bit message digest. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.

The core is designed for applications that need high throughput, low latency, and reduced power consumption.

Performance

The table below shows the logic resource and performance figures for the HMAC SHA-1 IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  HMAC SHA-1 Fast IP Core
technology Xilinx
Spartan 6-3
Altera
Stratix III-C2
Xilinx
Virtex 6-3
logic resources 394 slices
0 blockram
1024 ALMs
5 M9K
407 slices
0 blockram
max clock 205 MHz 304 MHz 400 MHz
max throughput
(per 512-bit hash)
1264 Mbps 1875 Mbps 2467 Mbps

 

Ordering Information

The HMAC SHA-1 IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Fast Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements HMAC SHA-1 keyed-hash message authentication specified by NIST FIPS 190-1
  • Synchronous 32/160-bit IO interface (byte oriented)
  • Pre-computation of internal key state for reduced latency
  • High throughput requires only 83* clock cycles per 512-bit hash block
  • Small hardware footprint for reduced power consumption
  • Quick key wipe for anti-tamper applications
Applications
  • Authenticated Encryption:
    Encrypt-then-MAC
  • Cryptographic Protocols:
    IPSec, Data Integrity & Authenticity (TLS/SSL)
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation

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