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HMAC SHA-256 Core

HMAC SHA-256 Core Pinout

Overview

The HMAC SHA-256 Fast IP Core provides a hardware implementation of the Keyed-Hash Message Authentication Code (HMAC) for the SHA-256 hash algorithm. The Fast IP Core provides a balance between high throughput and size and comes with a 32/256-bit IO interface. The HMAC SHA-256 can accept messages up to 264-512 bits in length and returns a 256-bit message digest. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.

The core is designed for applications that need high throughput, low latency, and reduced power consumption.

Performance

The table below shows the logic resource and performance figures for the HMAC SHA-256 IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  HMAC SHA-256 Fast IP Core
technology Xilinx
Spartan 6-3		 Altera
Stratix III-C2		 Xilinx
Virtex 6-3
logic resources 518 slices
0 blockram		 1251 ALMs
9 M9K		 570 slices
0 blockram
max clock 133 MHz 269 MHz 200 MHz
max throughput
(per 512-bit hash)		 1016 Mbps 2055 Mbps 1528 Mbps

 

Ordering Information

The HMAC SHA-256 IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Fast Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements HMAC SHA-256 keyed-hash message authentication specified by NIST FIPS 190-1
  • Synchronous 32/256-bit IO interface (byte oriented)
  • Pre-computation of internal key state for reduced latency
  • High throughput requires only 67* clock cycles per 512-bit hash block
  • Small hardware footprint for reduced power consumption
  • Quick key wipe for anti-tamper applications
Applications
  • Authenticated Encryption:
    Encrypt-then-MAC
  • Cryptographic Protocols:
    IPSec, Data Integrity & Authenticity (TLS/SSL)
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation