The HMAC SHA-384 Fast IP Core provides a hardware implementation of the Keyed-Hash Message Authentication Code (HMAC) for the SHA-384 hash algorithm. The Fast IP Core provides a balance between high throughput and size and comes with a 64/384-bit IO interface. The HMAC SHA-384 can accept messages up to 2128-1024 bits in length and returns a 384-bit message digest. For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
The core is designed for applications that need high throughput, low latency, and reduced power consumption.
The table below shows the logic resource and performance figures for the HMAC SHA-384 IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
HMAC SHA-384 Fast IP Core | |||
technology | Xilinx Spartan 6-3 |
Altera Stratix III-C2 |
Xilinx Virtex 6-3 |
logic resources | 1054 slices 0 blockram |
2438 ALMs 18 M9K |
1044 slices 0 blockram |
max clock | 114 MHz | 194 MHz | 166 MHz |
max throughput (per 1024-bit hash) |
1406 Mbps | 2393 Mbps | 2048 Mbps |
The HMAC SHA-384 IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..