Overview
The CTR AES Encryption/Decryption IP Core provides a balance between high throughput and size for the Counter (CTR) mode of operation. The IP core comes with either a 32-bit or 128-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need high throughput, low latency, and reduced power consumption.
For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.
Performance
The table below shows the logic resource and performance figures for the CTR AES Fast Encryption/Decryption IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
| CTR AES Fast Encryption/Decryption IP Core | |||
| technology | Xilinx Spartan 6-3 |
Altera Stratix III-C2 |
Xilinx Virtex 6-3 |
| logic resources | 514 slices 0 blockram |
559 ALMs 15 M9K |
496 slices 0 blockram |
| max clock | 228 MHz | 282 MHz | 380 MHz |
| max throughput (128-bit key) |
2432 Mbps | 3008 Mbps | 4053 Mbps |
Ordering Information
The CTR AES IP Cores are available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..