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OFB AES Core

OFB Core Pinout

Overview

The OFB AES Encryption/Decryption IP Core provides a balance between high throughput and size for the Output Feedback (OFB) mode of operation. The IP core comes with either a 32-bit or 128-bit IO interface and integrated key expansion supporting 128, 192, and 256-bit keys. The core is designed for applications that need high throughput, low latency, and reduced power consumption.

For additional security the core integrates a quick key wipe feature allowing the key to be erased both fast and securely.

Performance

The table below shows the logic resource and performance figures for the OFB AES Fast Encryption/Decryption IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  OFB AES Fast Encryption/Decryption IP Core
technology Xilinx
Spartan 6-3		 Altera
Stratix III-C2		 Xilinx
Virtex 6-3
logic resources 440 slices
0 blockram		 576 ALMs
15 M9K		 460 slices
0 blockram
max clock 232 MHz 284 MHz 384 MHz
max throughput
(128-bit key)		 2474 Mbps 3029 Mbps 4096 Mbps

 

Ordering Information

The OFB AES IP Cores are available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Features
  • Implements OFB mode of operation specified by NIST Special Publication 800-38A
  • Synchronous 32-bit and 128-bit IO interfaces
  • Integrated key expansion supporting 128, 192, and 256-bit key lengths
  • High throughput requires only 12, 14, and 16 clock cycles per encryption/decryption for the Fast IP core and 44, 52, and 60 clock cycles for the Standard IP core
  • Small hardware footprint for reduced power consumption
  • Quick key wipe for anti-tamper applications
Suitable for implementation in:
  • Authenticated Encryption:
    Encrypt-then-MAC
Applications
  • Open SSL
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation