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Home Products SHA-256 Fast IP Core

SHA-256 Core

SHA-256 Core Pinout

Overview

The SHA-256 Fast IP Core provides a hardware implementation of the Secure Hash Algorithm (SHA-256). The SHA-256 algorithm belongs to a group of five secure iterative hash algorithms recommended by NIST as part of their Secure Hash Standard (FIPS 180-3). The SHA-256 hash can accept messages up to 264-1 bits in length and returns a 256-bit message digest.

The SHA-256 Fast IP Core provides a balance between high throughput and size. The Fast IP core comes with a 32/256-bit IO interface and integrated padding logic. The core is designed for applications that need high throughput, low latency, and reduced power consumption.

Performance

The table below shows the logic resource and performance figures for the SHA-256 Fast IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  SHA-256 Fast IP Core
technology Altera
Cyclone V-C6
Xilinx
Virtex 6-3
Altera
Stratix III-C2
logic resources 881 ALMs
1 M10K
352 slices
0 blockram
819 ALMs
1 M9K
max clock 167 MHz 212 MHz 267 MHz
max throughput 1295 Mbps 1644 Mbps 2071 Mbps

 

Ordering Information

The SHA-256 Fast IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Fast Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements SHA-256 secure hash algorithm specified by NIST FIPS 180-3
  • Synchronous 32/256-bit IO interface (byte oriented)
  • Integrated padding logic
  • High throughput requires only 66 clock cycles per 512-bit hash block
  • Small hardware footprint for reduced power consumption
Suitable for implementation in:
  • Keyed-Hash Message Authentication Code: HMAC
  • Cryptographic Protocols: TLS/SSL and IPSec
Applications
  • IPSec, Data Integrity & Authenticity (TLS/SSL), Digital Signatures & Financial Transactions (DSS)
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation

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