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Home Products SHA-512 Fast IP Core

SHA-512 Core

SHA-512 Core Pinout

Overview

The SHA-512 Fast IP Core provides a hardware implementation of the Secure Hash Algorithm (SHA-512). The SHA-512 algorithm belongs to a group of five secure iterative hash algorithms recommended by NIST as part of their Secure Hash Standard (FIPS 180-3). The SHA-512 hash can accept messages up to 2128-1 bits in length and returns a 512-bit message digest.

The SHA-512 Fast IP Core provides a balance between high throughput and size. The Fast IP core comes with a 64/512-bit IO interface and integrated padding logic. The core is designed for applications that need high throughput, low latency, and reduced power consumption.

Performance

The table below shows the logic resource and performance figures for the SHA-512 Fast IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
 

  SHA-512 Fast IP Core
technology Altera
Cyclone V-C6
Xilinx
Virtex 6-3
Altera
Stratix III-C2
logic resources 1842 ALMs
2 M10K
761 slices
0 blockram
1604 ALMs
2 M9K
max clock 136 MHz 185 MHz 197 MHz
max throughput 1698 Mbps 2310 Mbps 2460 Mbps

 

Ordering Information

The SHA-512 Fast IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..

Product Briefs
Fast Core
Altera FPGA (pdf)
Xilinx FPGA (pdf)
Features
  • Implements SHA-512 secure hash algorithm specified by NIST FIPS 180-3
  • Synchronous 64/512-bit IO interface (byte oriented)
  • Integrated padding logic
  • High throughput requires only 82 clock cycles per 1024-bit hash block
  • Small hardware footprint for reduced power consumption
Suitable for implementation in:
  • Keyed-Hash Message Authentication Code: HMAC
  • Cryptographic Protocols: TLS/SSL and IPSec
Applications
  • IPSec, Data Integrity & Authenticity (TLS/SSL), Digital Signatures & Financial Transactions (DSS)
Deliverables
  • Device specific netlist or RTL Verilog/VHDL source code
  • Verilog/VHDL simulation model and testbench
  • User documentation

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