Overview
The SHA-512 Fast IP Core provides a hardware implementation of the Secure Hash Algorithm (SHA-512). The SHA-512 algorithm belongs to a group of five secure iterative hash algorithms recommended by NIST as part of their Secure Hash Standard (FIPS 180-3). The SHA-512 hash can accept messages up to 2128-1 bits in length and returns a 512-bit message digest.
The SHA-512 Fast IP Core provides a balance between high throughput and size. The Fast IP core comes with a 64/512-bit IO interface and integrated padding logic. The core is designed for applications that need high throughput, low latency, and reduced power consumption.
Performance
The table below shows the logic resource and performance figures for the SHA-512 Fast IP Core. Additional chipset figures as well as an operational data sheet are available upon request.
| SHA-512 Fast IP Core | |||
| technology | Altera Cyclone V-C6 |
Xilinx Virtex 6-3 |
Altera Stratix III-C2 |
| logic resources | 1842 ALMs 2 M10K |
761 slices 0 blockram |
1604 ALMs 2 M9K |
| max clock | 136 MHz | 185 MHz | 197 MHz |
| max throughput | 1698 Mbps | 2310 Mbps | 2460 Mbps |
Ordering Information
The SHA-512 Fast IP Core is available for licensing through Mercora Technologies. For more information on pricing options please contact a sales associate at This email address is being protected from spambots. You need JavaScript enabled to view it..